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About me

Posts

Future Blog Post

less than 1 minute read

Published:

This post will show up by default. To disable scheduling of future posts, edit config.yml and set future: false.

Blog Post number 4

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 3

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 2

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

Blog Post number 1

less than 1 minute read

Published:

This is a sample blog post. Lorem ipsum I can’t remember the rest of lorem ipsum and don’t have an internet connection right now. Testing testing testing this blog post. Blog posts are cool.

portfolio

publications

talks

Opt-Gen : An optimizing self generating optmizer for compilers

Published:

This was the end of thesis talk after the undergraduate research work. The project created an optimizer generated which generated data flow analyses based compiler optimization passes such as “Liveness Analysis”, “Constant Propogation and Folding”, “Available Expression Analysis”, “Anticipable Expression Analysis” and “Live Pointer Analysis” and inserted them in the compiler on the go. The framework also allowed users to provide their own data flow analyses equations and create custom optimization passes.

CUDA Task Launcher for CPU and GPU

Published:

This was an end of internship talk. For the summer research, I had investigated paths of enabling executing an unmodified CUDA application as-is on CPU SIMD units as well as on the GPU if the appliction and system demanded it to improve performance. This meant that if kernel offload costs were higher than the computation time then it made no sense to migrate tass to the GPU. However, we managed this in the system software layer transparent to the application developer. We showed performance enhancements of 1.5X compared to an only-CPU execution and 1.3X better to an only-GPU execution of data ceneter workloads.

Single Application Source, Any Hardware System

Published:

With growing heterogeneity, programmability without compromising performance is of utmost importance. This was research in investigating avenues to offload work on the underlying hardware - be it CPU or any accelerator - without making any changes to the application source code. i.e. An applcation written traditionally for an accelerator such as GPU in a specific language such as CUDA should be able to execute on a CPU if the data offload costs are not worth offloading an application from CPU to the accelerator without making any changes to the application source code to ease programmability while guaranteeing performance.

teaching

CPSC 323 : Introduction to Systems Programming(Spring 2021)

Undergraduate course, Yale University, Department of Computer Science, 2021

I was incharge of the compiler segment for this course. For this distribution I created and deployed a segment on introducing data flow analysis with liveness analysis and its application using register allocation. The segment consisted of creating an end to end assignment for register allocation and liveness analysis, a quiz and exam questions apart from study material which introduced the students to compilers.

CPSC 323 : Introduction to Systems Programming(Spring 2022)

Undergraduate course, Yale University, Department of Computer Science, 2022

I was again incharge of the compiler segment for this course. For this distribution I created and deployed an end-to-end toy compiler. We included introduction to the complete compiler flow focussing on the backend. The students had to implement three optimization passes (peephole, local and intra procedural) and code generation for a restrictive toy ISA that I came up with. The intention was to get students to write optimization passes and generate assembly to understand writing of assembly code apart from learning compilers.